Thanks for posting this! I recently looked into deciphering the circuit, but I think the conclusion is that the &FC7F register only supports the bank switching of the entire 32K static RAM when in 64K mode.Here's Sloggers MRB circuit diagram - reversed engineered by Prime (Phill Harvey-Smith).
As for the circuit, Y1 appears to yield a low level if an OS instruction is accessing "screen" memory (&3000-&7FFF inclusive) in 64K mode. Y2 yields a low level if an access to "screen" memory occurs in normal/turbo mode, and thus a high value if either 64K is enabled or if "turbo" memory (&0-&2FFF inclusive) is being accessed.
The ~RAMCS logic combines this and other things including the &FC7F setting, but the formulation of Y2 is what precludes "turbo" memory from being treated distinctly from "screen" memory in 64K mode. So, it isn't possible to have a routine in the lowest 8K (whether in DRAM or SRAM) reading from shadow RAM and writing to normal screen RAM with the hardware transparently mediate the accesses.
Statistics: Posted by paulb — Sun May 11, 2025 10:04 pm
