Apologies in advance. I suspect either I’m asking a question that’s already been very much answered before, or I’m opening a can of worms.
I’ve been doing a belated deep dive into the Beeb’s core ICs in order to improve my knowledge of electronics. At the moment, I’m sketching out an end to end logical flow of a complete memory access cycle, octal buffers onwards. But I’m struggling to piece together the granular details of the asynchronous DRAM access timings.
What I’m trying to do is draw a table of:
2MHz 4MHz 8MHz Event
Describing each step of a DRAM random access read. I’ve been looking at the datasheets and comparing to some Beeb technical info but I’m not clear on the timing aspects for placing the row and column addresses on A6-0, /RAS, /CAS, /WE, data out.
Is it something like this?
X 0 0 Row Address on A6-0, RAS high, CAS high
X 0 1 Row Address on A6-0, RAS low, CAS high
X 1 0 Column Address on A6-0, RAS low, CAS low
X 1 1 RAS high, CAS low, Buffer Data Out
One issue I have is the slight delay apparently needed between putting a valid address on A6-0 and then doing the strobe. I can’t figure out how exactly this latency fits into the above. Does anyone have the precise 8MHz phase-accurate timings? Does this address-strobe latency have anything to do with the ‘2MHz E’ clock signal derived from the 6502’s delayed and inverted PHI1 output? Has anyone probed the signals on a scope to see what precisely happens when?
EDIT: And it should all happen during one phase of the 2MHz clock! Melted brain.
Many thanks in advance!
I’ve been doing a belated deep dive into the Beeb’s core ICs in order to improve my knowledge of electronics. At the moment, I’m sketching out an end to end logical flow of a complete memory access cycle, octal buffers onwards. But I’m struggling to piece together the granular details of the asynchronous DRAM access timings.
What I’m trying to do is draw a table of:
2MHz 4MHz 8MHz Event
Describing each step of a DRAM random access read. I’ve been looking at the datasheets and comparing to some Beeb technical info but I’m not clear on the timing aspects for placing the row and column addresses on A6-0, /RAS, /CAS, /WE, data out.
Is it something like this?
X 0 0 Row Address on A6-0, RAS high, CAS high
X 0 1 Row Address on A6-0, RAS low, CAS high
X 1 0 Column Address on A6-0, RAS low, CAS low
X 1 1 RAS high, CAS low, Buffer Data Out
One issue I have is the slight delay apparently needed between putting a valid address on A6-0 and then doing the strobe. I can’t figure out how exactly this latency fits into the above. Does anyone have the precise 8MHz phase-accurate timings? Does this address-strobe latency have anything to do with the ‘2MHz E’ clock signal derived from the 6502’s delayed and inverted PHI1 output? Has anyone probed the signals on a scope to see what precisely happens when?
EDIT: And it should all happen during one phase of the 2MHz clock! Melted brain.
Many thanks in advance!
Statistics: Posted by Arx — Sun Feb 16, 2025 12:00 am